11/17 [2bit比較器 behavior , RTL 和 gate_level ]

2bit behavior compare

2bit RTL compare

2bit gate_level compare

11/17加分考吶 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

10/27考試前一周

10/20上課教學-3

module top;
wire x_in1,x_in2,x_in3,x_in4;
wire y_out;

system_clock #200 clock1(x_in1);
system_clock #150 clock2(x_in2);
system_clock #100 clock1(x_in3);
system_clock #50 clock2(x_in4);


A01_4_Unit AH1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodule

module A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;
and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);

endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

10/20上課教學-2

module A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;
output y_out;wire y1,y2;

reg y_out,y1,y2;

always
begin
#1 y1=x_in1&x_in2;
#1 y2=x_in3&x_in4;
#1 y1=x_in1 nor x_in2;
end

endmodule

10/20上課教學-1

module A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;wire y1,y2;

and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);

endmodule

10/13新教室的第二次上課

半加法器

module top;
wire a,b;
wire sum,c_out;

system_clock #100 clock1(a);
system_clock #50 clock2(b);

Add_half AH1(sum,c_out,a,b);

endmodule

module Add_half(sum,c_out, a, b);

input a,b;
output sum,c_out;
wire c_out_bar;

xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

10/6新教室

第一節在做作業
第二節在講上禮拜的
第三節在上新的要延續下禮拜
http://dyu9502.blogspot.com/<---老師網址
題目:Design a verilog model of a adder and write a testbench to verify the designed verilog model
p.q:
module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

9/22課堂作業

第一次作業

module top;
wire a,b;
reg c;
System_clock #100 clock1(a);
System_clock #50 clock2(b);
always#1 c=a&b;
endmodulemodule System_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if ($time>1000)#(PERIOD-1)$stop;
endmodule



還不賴這堂課
有趣極了