module top;wire a,b;
reg c;
System_clock #100 clock1(a);
System_clock #50 clock2(b);
always#1 c=a&b;
endmodulemodule System_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if ($time>1000)#(PERIOD-1)$stop;
endmodule
還不賴這堂課
有趣極了
